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Altera_Forum's avatar
Altera_Forum
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13 years ago

SDRAM Controller-Problem

Hi,

i build a design in SOPC Builder on Quartus 8.0 (CycloeIII) that looks like this :

[CPU]<------->[Half rate bridge]<--------->[SDRAM Controller(not DDR)].

66MHz 133MHz

I've got the problem that it does not work.My "Hello World" will not be monitored.

It seems like the that the SDRAM Controller does not support 133 MHz.

i want to put later a DMA controller connected to the Bridge to transfer my data.

Can somebody tell me if i am rigth and if there is a possibility to work around .

Thanks

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Are You sure Your SDRAM chip itself support such speed? Also are You sure, that all setup and hold timings are correct? Does it work with slower clock speed? E.g. 75MHz?

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    thanks Socrates for your quickly reply.

    no i have not test it for 75 MHz.As in the datasheet it runs up to 166 MHz(dependent from speed grad).Timing are setting and are correct.

    I ve found something strange:I've made a mistake an put the 1/2rate Bridge master to the sysclk(66 MHz) and it works.I can send data through to the sdram.But that is not normal,because the bridge master must runs at the same frequency(and twice sysclk) as the slave. Can u have an explanation about this?

    thanks.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I don't see any problems here. This setup should run fine. What's the memory bus width of the SDRAM chip itself?

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Try to remove the bridge and let the interconnect to create a hand-shake algorithm to use the SDRAM. I believe 133MHz is just too fast. Try to use 66MHz for the SDRAM chip and 33MHz for the rest of the system before trying that solution I've mentioned before.