Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorSDRAM Controller-Problem
Hi, i build a design in SOPC Builder on Quartus 8.0 (CycloeIII) that looks like this : [CPU]<------->[Half rate bridge]<--------->[SDRAM Controller(not DDR)]. 66MHz ...
Altera_ForumHonored Contributor
Honored Contributorthanks Socrates for your quickly reply.
no i have not test it for 75 MHz.As in the datasheet it runs up to 166 MHz(dependent from speed grad).Timing are setting and are correct. I ve found something strange:I've made a mistake an put the 1/2rate Bridge master to the sysclk(66 MHz) and it works.I can send data through to the sdram.But that is not normal,because the bridge master must runs at the same frequency(and twice sysclk) as the slave. Can u have an explanation about this? thanks.
