SDRAM Controller Intel FPGA IP not working as expected

Hi Adzim,

thanks for your answer!

Some flaw in my timing settings was my first idea. I checked it twice and couldn't find one. I was hoping that somebody could take a look at my settings to see if I miss something. (Visible in the last screenshots).

That's the SDRAM mounted on the board:

And that's the doc I used (it's the online version of the pdf attached to the CD): https://www.issi.com/WW/pdf/42-45R-S_86400D-16320D-32160D.pdf

While writing this I realized that on the photo there is an 'F' as last character visible not a 'D' as in the CD docs. I couldn't spot any difference timing wise, but to be sure that's the one with an 'F':

https://www.issi.com/WW/pdf/42-45R-S_86400F-16320F.pdf

I want to point out that the "only" problem is that the read valid signal is not reliable. The data itself seems to be correct.
I write values from 0 to 4095 and I get values from 0 to 4095, but I would expect the read valid signal to go down one clock cycle after one value was spit out and only go on again when the next one is there.
As you can see in the screenshot of Signal Tap, the read valid signal stays high although there is still the first 0 visible.

Am I misunderstanding the meaning of readvalid?

I just tried the "SDRAM_RTL_Test" design and I suppose it works as expected.

LEDR 0 is on constantly .
LEDR 1 blinks at first and then stops to be constantly on too.
LEDR 2 blinks all time

I couldn't understand the purpose of LEDR 0 but as far as I understood, LEDR 1 blinks as long as the test runs and then is either constantly on to show success (or goes off to show failure).
LEDR seems to be a heartbeat and is only constantly on if KEY 0 is pressed.

regards,

Tim