Hi, I have developed my own SDR SDRAM controller in VHDL to integrate it with the rest of a design inside a Cyclone IV for image processing. By testing the controller I write in the SDRAM 307200 consecutive bytes using a known pattern. When I read the SDRAM most of the bytes are read correctly but there are small areas in the RAM that corresponding bytes are read with errors. When I read again the RAM some of the previous error locations are read correctly and some other locations that have been read without errors the first time now are read with errors. By reading again and again, error locations change randomly (at least randomly it seems to me). Does this problem look familiar to anyone? Any idea where should I look for a solution? Thanks in advance. Regards, John

Hi John, --- Quote Start --- Does this problem look familiar to anyone? Any idea where should I look for a solution? --- Quote End --- Since you made no comments about the design meeting timing, that is where I would first look. You need to constrain the FPGA pins so that the control signals from the FPGA to the SDR meet timing, and so that the data bus meets timings for both write and read. Cheers, Dave

Thanks for your answer. I have chosen loose timing requirements so I believe I would have no issue on that and that's why I did not mention it at all. I have also checked signals at the oscilloscope and by sending always the byte 0x00 and sometimes I see that some wires of the data bus become logic '1' instead of staying always at logic '0' as the stored data would have been logic '1'.

--- Quote Start --- I have chosen loose timing requirements so I believe I would have no issue on that and that's why I did not mention it at all. --- Quote End --- You don't get to chose the timing requirements, you must meet the timing requirements stated in the SDR data sheet. You can make your timing requirements easier to meet by using a lower clock frequency to the SDR. However, you still need to meet refresh timing requirements. Cheers, Dave

Noting that you have written your own SDRAM controller, have you included refresh behavior? If not, it would be best to go back and re-read the SDRAM datasheet. You will also need to constrain the timing so your design will synthesize properly. If you do not constrain your design, it will most likely not function properly.

Hi John, Let's say your design must comply with two sets of timing requirements: - SDRAM timing specification itself, namely row precharge time, data latency, refresh period, and so on. This is sort of 'functional' timing and depends uniquely on your hdl code. - FPGA timing; you must make sure all sdram signals generated by fgpa mantain a good synchronization across routing and i/o pins, namely they have no excessive skew or trasmission delays. For this part, you need to carefully constrain your design.

SDR SDRAM controller problem | Altera Community

13 Replies

Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

I have chosen loose timing requirements so I believe I would have no issue on that and that's why I did not mention it at all.

--- Quote End ---

You don't get to chose the timing requirements, you must meet the timing requirements stated in the SDR data sheet.

You can make your timing requirements easier to meet by using a lower clock frequency to the SDR. However, you still need to meet refresh timing requirements.

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
Thanks for your answer.
I have chosen loose timing requirements so I believe I would have no issue on that and that's why I did not mention it at all.

I have also checked signals at the oscilloscope and by sending always the byte 0x00 and sometimes I see that some wires of the data bus become logic '1' instead of staying always at logic '0' as the stored data would have been logic '1'.
Altera_Forum
Honored Contributor
14 years ago
Hi John,

--- Quote Start ---

Does this problem look familiar to anyone?
Any idea where should I look for a solution?

--- Quote End ---

Since you made no comments about the design meeting timing, that is where I would first look.

You need to constrain the FPGA pins so that the control signals from the FPGA to the SDR meet timing, and so that the data bus meets timings for both write and read.

Cheers,
Dave

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SDR SDRAM controller problem

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