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Honored Contributor
Honored ContributorSDR SDRAM controller problem
Hi, I have developed my own SDR SDRAM controller in VHDL to integrate it with the rest of a design inside a Cyclone IV for image processing. By testing the controller I write in the SDRAM 307...
Altera_ForumHonored Contributor
Honored ContributorHi John,
--- Quote Start --- Does this problem look familiar to anyone? Any idea where should I look for a solution? --- Quote End --- Since you made no comments about the design meeting timing, that is where I would first look. You need to constrain the FPGA pins so that the control signals from the FPGA to the SDR meet timing, and so that the data bus meets timings for both write and read. Cheers, Dave
