Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

SDR SDRAM controller problem

Hi, I have developed my own SDR SDRAM controller in VHDL to integrate it with the rest of a design inside a Cyclone IV for image processing. By testing the controller I write in the SDRAM 307...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thanks for your answer.

I have chosen loose timing requirements so I believe I would have no issue on that and that's why I did not mention it at all.

I have also checked signals at the oscilloscope and by sending always the byte 0x00 and sometimes I see that some wires of the data bus become logic '1' instead of staying always at logic '0' as the stored data would have been logic '1'.