Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorSDR SDRAM controller problem
Hi, I have developed my own SDR SDRAM controller in VHDL to integrate it with the rest of a design inside a Cyclone IV for image processing. By testing the controller I write in the SDRAM 307...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I have chosen loose timing requirements so I believe I would have no issue on that and that's why I did not mention it at all. --- Quote End --- You don't get to chose the timing requirements, you must meet the timing requirements stated in the SDR data sheet. You can make your timing requirements easier to meet by using a lower clock frequency to the SDR. However, you still need to meet refresh timing requirements. Cheers, Dave
