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Altera_Forum's avatar
Altera_Forum
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13 years ago

SDR SDRAM controller problem

Hi, I have developed my own SDR SDRAM controller in VHDL to integrate it with the rest of a design inside a Cyclone IV for image processing. By testing the controller I write in the SDRAM 307...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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I have chosen loose timing requirements so I believe I would have no issue on that and that's why I did not mention it at all.

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You don't get to chose the timing requirements, you must meet the timing requirements stated in the SDR data sheet.

You can make your timing requirements easier to meet by using a lower clock frequency to the SDR. However, you still need to meet refresh timing requirements.

Cheers,

Dave