SDC for ALTCLKCTRL

I'm not sure what you mean by fails to recognize. The altclkctrl is basically a mux, and the clocks all pass through it and are analyzed. This is the way it would work if you built a mux out of logic. The real problem is that timing analysis assumes all clocks can happen at the same time, so you'll get an analysis where pin1 goes through the mux and feeds the source register and pll_clk1 goes through the mux and feeds the destination(which in theory could happen when you switch clocks). Just adding the generated clocks doesn't change this analysis. Instead, it gives you a clear clock name that you can use for your set_clock_groups.

As a test, before adding the generated_clocks, do a report_timing on some paths that are fed by this altclkctrl and see what it analyzes. If this was a clock that wasn't recognized, you wouldn't get any analysis, but I suspect you will.

(In theory, you could skip doing the generated clocks and probably just do a set_clock_groups with the four clocks that drive into the altclkctrl, and probably be fine. The only way this wouldn't work is if you had paths that were outside of the altclkctrl you wanted to analyze, e.g. if you had a path who's source register is directly driven by pll_clk1 and destination is driven by pll_clk2 you might not want to cut that, but still would want to cut the analysis between these two clocks when they go through the altclkctrl block.)