Occasional Contributor
Regular ContributorI was not intending to provide THE solution to your problem, only HOW I implemented my solution, to show how to apply SDC constraints. I did not intend it to be a cut and paste solution for you.
In my particular case, there are two memories on the same bus, an internal memory implemented via block rams, and an external memory implemented in the 256KB async SRAM device attached to the FPGA. There was not enough internal block ram available to build the entire memory (32K x 12 bit) using internal block ram, so I split it and have the low 8K internal, the upper 24K external.
Yes, the md lines are assigned twice, as a tri-state bus with mutually exclusive enable signals.
Yes, mdo is a register that only clocks the output data of the internal block ram.
md lines are registered at the next higher level to this module (at the posedge of clk).
The timing setup/hold numbers were based on the data sheet specs of the SRAM device on the board.
Multicycle is 2 since it is not realistic to drive a 10ns access SRAM device using a 12.5ns clock period.
If you believe you can meet timing using a 10ns device on a 20ns clock period, then you only need set_input_delay and set_output_delay. No multicycle_path statement needed.
Occasional Contributor
@ak6dn wrote:
I was not intending to provide THE solution to your problem, only HOW I implemented my solution, to show how to apply SDC constraints. I did not intend it to be a cut and paste solution for you.
Oh, man, I'm sorry. This is my bad english. I don't mean you should provide a copy-paste solution for me.
I mean I don't understand how your solution works, so I can't use it to produce my solution )
@ak6dn wrote:
md lines are registered at the next higher level to this module (at the posedge of clk).
Multicycle is 2 since it is not realistic to drive a 10ns access SRAM device using a 12.5ns clock period.
If you believe you can meet timing using a 10ns device on a 20ns clock period, then you only need set_input_delay and set_output_delay. No multicycle_path statement needed.
Sounds more reasonable to me. So you keep registering data at posedge, but wait 1 extra period of clk before actually using data?
Well, I can lower the frequency too, I just don't want to do this.
@ak6dn wrote:
The timing setup/hold numbers were based on the data sheet specs of the SRAM device on the board.
How they are based? I tried to use some formulas from google, but got a nonsense.
