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Vic3Dexe's avatar
Vic3Dexe
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

SDC constrains for async static RAM

I have async static RAM with 10 ns access time. I try to read data from it in such a way, that address formed in one register, then data latched to another, both have the same clock 50 MHz (20 ns)....
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Could you try put your data_reg at the I/O? This would reduce the delay.


Regards,

Nurina


  • Vic3Dexe's avatar
    Vic3Dexe
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago
    @Nurina wrote:

    Could you try put your data_reg at the I/O? This would reduce the delay.

    I will try, thx.