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Altera_Forum's avatar
Altera_Forum
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15 years ago

RTL of design is different from expected

I would like to implement a freq divider by using clock enable method(clock enable signal connect to every enable pin of register in design). however, when i write the verilog code e.g "...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

rbugalho,

If doing like this, it will lost the function of one input signal. As we know, when clk_ena is low, output will maintain the previous data. When function_ena is low, output will be low as well.

Anyway, i have tried the method u proposed. I fail to find the my_clk_en. Besides, the enable pin of register is not connected to anything