Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Rise fall time I/O LVTTL EP2C5T144C8N

Hello forum members,

I am currently in the process of designing a PCB with the EP2C5T144C8N but am facing uncertainties regarding the rise fall time of the I/O (as output).

The reason I want to know the rise/fall time is because I need to know whether I need to treat the I/O traces as transmission lines.

Obviously it would be preferable to do so regardless of trace length or rise / fall time but that demands a thinner PCB to ensure that the traces don't become so thick that they overlap (to get the correct trace impedance). Thinner PCBs are also more expensive..

I have already checked "Timing Specifications" in the "Cyclone II Device Handbook" but could not see the information I wanted.

My setup:

165 MHz LVTTL output 3.3V connected to a chip with 1.5 pF input capacitance

My question:

What is the rise / fall time of the output of the fpga and how can I find this information?

Thank you very much,

Prodigity

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Detailed information about static and dynamic output characteristics can be found in the Cyclone III Ibis file. For higher current strengths, you can assume rise times in the range of 0.5 ns. Every trace longer than a few cm has to be treated as transmission line in this case.

    I don't agree however with the consideration about board thickness.

    A typical FPGA board is 6 layers and above, 4 layer can work for simple designs with few low interconnect count. You can easily implement transmission lines in the 50 to 70 ohms (nominal) range. There is not need for exact impedance matching and impedance controlled manufacturing, just systematically designed impedances that are kept within +/- 20 or even 30 % tolerance to reduce reflections.

    For CMOS/LVTTL I/O standard, source side series termination is usually the best option.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hello FvM, thank you for your helpful post. +1 rep

    My traces are 2.5 cm long so with a rise time of 0.5 ns I figure that I don't necessarily need to treat them as transmission lines.

    However seeing as my design already uses source side series termination I'll just change their value to match the impedance

    of the traces (70 Ohm).

    Thank you very much!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    After my last post I was planning to place the termination resistor because I thought it could not do any harm,

    the LTspice simulation however has convinced me it is more of a necessity then I originally conceived.

    The cyclone handbook states it can handle overshoot of up to 4.5V at 10% duty cycle, but that is just too close for comfort.

    It seems wise to leave room for error..

    Thank you for providing me with these insights :)