Rise fall time I/O LVTTL EP2C5T144C8N

Detailed information about static and dynamic output characteristics can be found in the Cyclone III Ibis file. For higher current strengths, you can assume rise times in the range of 0.5 ns. Every trace longer than a few cm has to be treated as transmission line in this case.

I don't agree however with the consideration about board thickness.

A typical FPGA board is 6 layers and above, 4 layer can work for simple designs with few low interconnect count. You can easily implement transmission lines in the 50 to 70 ohms (nominal) range. There is not need for exact impedance matching and impedance controlled manufacturing, just systematically designed impedances that are kept within +/- 20 or even 30 % tolerance to reduce reflections.

For CMOS/LVTTL I/O standard, source side series termination is usually the best option.