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Hi msj. I use phy Marvell 88E1111-BAB-1000 (on my own board) and Micrel KSZ9021RL/RN (on Terasic Cyclone V kit). This chips has internal DLL for TX and RX path (to MAC). Micrel's DLL is cool and magic! You may set CLK to Data and Clk to CTL delay with 0.2 ns precision!
Register 260 (104h) - RGMII Clock and Control Pad Skew
260.11:8 rxdv_pad_skew RGMII RX_CTL PAD Skew Control (0.2ns/step) 0111
260.7:4 txc_pad_skew RGMII TXC PAD Skew Control (0.2ns/step) RW 0111
260.3:0 txen_pad_skew RGMII TX_CTL PAD Skew Control (0.2ns/step) RW 0111
Register 261 (105h) - RGMII RX Data Pad Skew
261.15:12 rxd3_pad_skew RGMII RXD3 PAD Skew Control (0.2ns/step) RW 0111
261.11:8 rxd2_pad_skew RGMII RXD2 PAD Skew Control (0.2ns/step) RW 0111
261.7:4 rxd1_pad_skew RGMII RXD1 PAD Skew Control (0.2ns/step) RW 0111
261.3:0 rxdO_pad_skew RGMII RXD0 PAD Skew Control (0.2ns/step) RW 0111
You may see Altera an477 about constraining RGMII. Try use LogicLock option. See Timequest. My project report:
http://www.alteraforum.com/forum/attachment.php?attachmentid=11840&stc=1 . Difference between lines must be <<1ns! (My project for Cyclone V and my own board)
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Hi Alex.
Can you copy/paste your scd file to constraints the rgmii interface of the marvell chip?
I have problems with cyclone5 and marvell PHY input constraints.
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