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Altera_Forum
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10 years ago

RGMII Source Synchronous Timing Problem

Hi design: My design interfaces an RGMII Gigabit Ethernet running at 125 MHz with 4 bits of data and 1 bit for validity of data. Data & clock are edge-aligned at the PHY output ports: Da...
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Altera_Forum
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10 years ago

Thank you Alex310. Micrel PHY MDIO ports can be driven in order to adjust IO timing as you reminded and it may resolve the problem; Nevertheless it works in some situations without PAD skew adjustment. LogicLock option could be a solution, if you are sure everything is correct. I want to know how to verify timing on every synthesis run. This is my problem. I have studied TimeQuest manuals and AN477. As I mentioned the report_timing command does not tell me if timings are met.