RGMII Source Synchronous Timing Problem

Actually there is a MAC inside FPGA, but I have problem in capturing correct PHY data. Other parts of design have been removed temporarily. You can direct clock to the MAC if the PHY data is center-aligned. In my case (Micrel PHY) data & clk are edge-aligned, so a PLL phase shift is necessary.

My design works on a simpler project with no phase shift, but when it comes to a large design it does not. Timing should be checked and I don't know how to do that. The report_timing command finds no setup path and I don't know why!