Reset Vector - NIOS

It's based off the base address you set in Platform Designer. So it looks like in PD you have this flash set at address 0x10000000. You set the offset to 0x08b00000, so the Nios accesses the flash starting at 0x18b00000.

1) Yes.

2) Yes and yes.

3) Nowhere. The code is sent over JTAG via the debugger.

4) No clue without knowing what your code is doing.

Hi,

I agree with sstrell's statement:

1)The Nios processor code will be stored in the flash memory pointed by the reset vector offset address

2)Nios processor code starts at 0x08b00000

3)The code is sent over JTAG via the debugger and not stored in any location

Thank you.

Regards,

Kelly

Thanks for the clear explanation.

I would like to reopen this thread with further question on reset vector for Nios.

Q1) You have mentioned Nios access the flash starting at " 0x18b0_0000". Does this 0x18b0_0000 represent an address present in Flash?.

Here is the picture of the platform designer for my system.

Here is a picture from the board test gui that has come along with the development kit. The gui mentions that the flash address is only between 0x0000_0000 to 0x0FFF_FF80.

And the QSF of this project shows only 26 address lines for the flash. so what is the actual memory of the flash we are talking about here?

note that the project can compile fine, and the nios can boot up, and TCP is up and running.

Q2) what does the reset vector address actually signify?. Does pointing the reset address vector to 0x18b0_0000 and choosing the reset vector memory as "ext_flash.uas" change/write something to the flash?. what does this address location denote?.

Note that we just pointed out this reset vector location to the non volatile memory, but then we only generate SOF, and program into the FPGA. never generated any pof or flash specific file. So, it makes me wonder what this reset vector actually signifies, and how come it works even if we point the reset vector memory to flash, despite not programming anything to flash!.

p.s: please feel free to write back with more questions incase if my statements or questions are not clear. I am happy to explain.

Thanks

1) As already stated, the flash in your system starts at 0x10000000 and verified in the address map you've shown. The offset you've selected for the reset vector must be within the range of the flash, and it is. The board test system is a completely different design so its setup doesn't apply to your design. Addressing is specific to the host you connect to, in this case, the Nios processor.

2) This is the address where the Nios will start running code from. It doesn't do anything to the flash. The flash (or whatever memory is attached) must be set up appropriately to start running code at that address. On the dev kit, the flash is already configured though you can change it if you want to using the flash programmer tool in Quartus.

Hi MK,

1) The flash in your system starts at 0x10000000 and verified in the address map with your attached screenshot. The offset you selected for the reset vector must be within the range of the flash, and it is.

The board test system is a different design so it is not compatible to your design. Addressing is specific to NIOS processor, which is also your host..

2) This is the address where the NIOS will start running code from and the flash will not be affected. The flash (and the memory that are attached in screenshot of GUI) must be set correctly to start running code from that address.

The flash is already configured on the Development Kit but you can still change it by using the flash programmer tool in Quartus.

Hope this clarifies your doubts.

Thank you.

Regards,

Kelly

Hello,

"This is the address where the Nios will start running code from. It doesn't do anything to the flash."

"This is the address where the NIOS will start running code from and the flash will not be affected."

-- When you say the Nios will start running the code from that specific address location, then doesn't it mean that there should be something written to that address location in flash?. What is the meaning of running the code from that address?. I would think a piece of code is copied to starting from that specific address location and then start running the code. Can you throw a bit more light on this?

So my confusion is the following :

1) If I set the nios reset vector to a flash address, then as per my understanding, there has to be a code there on the flash at that address. The piece of code which is mentioned here is the .pof or some equivalent file of the design in flash, with nios in it. The system that I am building in Qsys will be eventually converted into a bit stream, and then loaded into the flash. This is the same piece of code that the reset vector points to. Am I correct?

2) The reset vector address is set as 0x18b00000 and the flash base address is set as 0x10000000, and you have mentioned "So if the flash is set to be at that address, there has to be code there on the flash at that address". So as per flash address, we need 28 address lines to map to 0x1000_0000 ( converted this to binary and the 28th bit high. But, as per the development kit schematic, there are only 27 address lines as per schematic. p.s: see below. So how is the address 0x1000_0000 accessed? There is no such address in flash memory.

The above two questions are for one specific design that I worked with.

The following questions are for a completely different design. But the question is related to reset vector, and using external flash as reset vector memory.

Q1) Does the reset vector specify any value for reset to nios core?, apart from mentioning the starting location of the code?

Q2) In this specific new project, I specified the reset vector to point to external flash. I just generated a sof and programmed only my FPGA, and the design was still working. I never touched the flash. So how did this design work?. I pointed the reset vector to external flash, and i never programmed the flash, but just loaded the fpga with sof, opened eclipse, ran my software project in NIOS, and NIOS was able to boot up and perform the required TCP server action. So I am confused on how did this even boot up and work in the first place?.

Thanks