Hello,
I have a reference NIOS project in which the reset vector memory is selected as an external flash. I opened platform designer and found the following information. Picture attached below.
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There is not specific reason why it is greyed out. It is according to the base address you set in Platform Designer. You have the flash address set to 0x10000000, and the offset to 0x08b00000. Therefore, flash will start access at 0x18b00000.
1) If I set the nios reset vector to a flash address, then as per my understanding, there has to be a code there on the flash at that address. The piece of code which is mentioned here is the .pof or some equivalent file of the design in flash, with nios in it. The system that I am building in Qsys will be eventually converted into a bit stream, and then loaded into the flash. This is the same piece of code that the reset vector points to. Am I correct?
2) The reset vector address is set as 0x18b00000 and the flash base address is set as 0x10000000, and you have mentioned "So if the flash is set to be at that address, there has to be code there on the flash at that address". So as per flash address, we need 28 address lines to map to 0x1000_0000 ( converted this to binary and the 28th bit high. But, as per the development kit schematic, there are only 27 address lines as per schematic. p.s: see below. So how is the address 0x1000_0000 accessed? There is no such address in flash memory.
The above two questions are for one specific design that I worked with.
The following questions are for a completely different design. But the question is related to reset vector, and using external flash as reset vector memory.
Q1) Does the reset vector specify any value for reset to nios core?, apart from mentioning the starting location of the code?
Q2) In this specific new project, I specified the reset vector to point to external flash. I just generated a sof and programmed only my FPGA, and the design was still working. I never touched the flash. So how did this design work?. I pointed the reset vector to external flash, and i never programmed the flash, but just loaded the fpga with sof, opened eclipse, ran my software project in NIOS, and NIOS was able to boot up and perform the required TCP server action. So I am confused on how did this even boot up and work in the first place?.
1) You're getting the programming bitstream and processor code mixed up. You must have a .pof or something in some non-volatile memory to program the device itself and then you need the Nios processor code stored somewhere else, pointed to by the reset vector, to start running that code when the processing starts (or is reset).
2) You're forgetting the CE signal. And the 0x10000000 is the base address in the system design, not a physical address on the flash. That goes back to the offset value to access the physical location on the flash.
3) No, starting location of code.
4) Your code is running directly from Eclipse (debug mode) over the JTAG connection. Eventually, you have to put the code in flash (or wherever specified by the reset vector).
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