reset sync design logic

I have a question regarding reset sync logic .

first of all what I understood about requirement of reset synchronization in design :

- Reset will be asynchronous in nature.

- It is not an issue if reset assertion in design will not be on active edge.

- But when de-asserting reset at that time it must be on active edge of clock.

- If de-assertion is asynchronous in nature then it may case design output to stuck into metastable-state

- So to prevent it reset synchronize is used.

( I would request to all member to clarify me about need of reset synchronize if i understood something wrong !!! )

- When I google about how to design reset synchronize module I just confused with the way they have synchronize reset with clock.

//==================================================================================================================================

// reset synchronize logic snippet I found from website

//==================================================================================================================================

module reset_synchronize

(

input clock_i,

input resetn_i,

output sync_resetn_o

);

logic resetn_f1;

logic resetn_f2;

assign sync_resetn_o = resetn_f2;

always_ff @(posedge clock_i or negedge resetn_i)

begin

if(~resetn_i)

begin

resetn_f1 <= 0;

resetn_f2 <= 0;

end

else

begin

resetn_f1 <= 1'b1;

resetn_f2 <= resetn_f1;

end

end

endmodule

//==============================================================================================================

// what I observed from above snippet & my question

//==============================================================================================================

- have used two flip-flops ( no idea for what they have used second flip-flop as my reset will sync only need 1 flip-flop )

- when reset_n is there will be keeping "resetn_f1" & "resetn_f2" zero ( I am okey with this !! )

- when reset_n = 1 then will be giving "resetn_f1 == 1" & "resetn_f2 = resetn_f1"

Q1 : whay they have used "resetn_f2" as with simple "resetn_f1" also I can have de-assertion of reset_n on clock edge.