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@ Kaz,
According to me, we must reset second register also. Consider the case when clock has been lost due to some issue and meantime, we need to reset our design. In this case, if we do not use reset for second register, our design will not get reset. So, by using reset for second register, we ensure that 'asynchronous' assertion benefit of reset ( design can be reset even in the absence of clock ) is preserved.
Feel free to share your thought.
Thank you,
Bhaumik
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That makes perfect sense. It also explains why reset synchroniser is safer than just passing reset through D input(data synchroniser)
Thanks for sharing
Honored Contributor
