Reset for PLL

I am working on a project involving Arria V FPGA.

I need to have a PLL for generating clocks for my internal FPGA logic.

I am confused about the reset signal of PLL. I have no external H/W reset pin. To which pin must I connect this reset signal.

I am deriving the reset signal for logics from PLL locked signal.

I am thinking of connecting this pin to POR signal. How to access the power on reset pin?

Are there any other suggestions for connecting PLL reset pin?

Thanks