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Honored Contributor
Honored ContributorReset for PLL
I am working on a project involving Arria V FPGA. I need to have a PLL for generating clocks for my internal FPGA logic. I am confused about the reset signal of PLL. I have no external H/W reset...
Altera_ForumHonored Contributor
Honored ContributorI don't know Arria V, but with other Altera FPGA devices the PLL reset signal is optional.
You expose and connect it only in special situation, i.e. when you need to reconfigurate the PLL or when you switch off a clock and have to resynchronize.
