Remote update Flash EPROM (EPCS16) using lan/ uart

I have some questions yet:

1) How can i guarantee that reconfig from nios takes 500ns and more, when i set reconfig to "1" and it should cause restart all fpga chip (in next clock edge) ?

2) These other pins dont need to connect to some vcc or gnd ? (design.png)

3) And in Technology Map Viewer the design of altremote megafunction hasnt connected pin reconfig ? ...

Is somewhere simple design with nios, epcs and sltremote megafunction for cyclone III ?

Thank you for answer.

I am sorry, it was my and Quartus error. When i erase and include the altremote megafunction and connect to nios2 through another port (enable_bus), it works OK.

Jan

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I am sorry, it was my and Quartus error. When i erase and include the altremote megafunction and connect to nios2 through another port (enable_bus), it works OK.

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Yes, you can see that the !RCONFIG input is unused (connected to 1) in the netlist of your previous post.

Good that it works.

Yes, now, when i start from 0x0 address it works.

But i have new question. I possible to start reconfig from flash eprom from 0x00|10|00|00 = 1MB ? How ?

I have code, which write to the flash from 1MB over (0x00100000-0x001FFFFF) and after this i try to start from address 1MB:

-----------------------------------------------------------------------------

printf("Set boot address 0x100000.\n");

// i must shift the address 0x00100000 to the right 2 bits

IOWR_ALTERA_AVALON_PIO_DATA(ENABLE_BUS_BASE,0x00040000);

usleep(1000);

printf("Write the boot address 0x100000.\n");

// address + param + write

IOWR_ALTERA_AVALON_PIO_DATA(ENABLE_BUS_BASE,0x00040000|0x01000000|0x02000000);

usleep(1000);

printf("Start reconfiguration.\n");

IOWR_ALTERA_AVALON_PIO_DATA(ENABLE_BUS_BASE,0x80000000);

-------------------------------------------------------------------------

but it start again from 0x0.

Where could be error ?

Or is there only one possibility and it is to start from 0x0 ? (in altremote_ug or an521 it looks, that it could be able, but exact description, how to make it, i didnt find.)

Thank you for your answer.

Jan

In attachment i include the connected altremote_megafunction.

For an Nios based RSU example, you can also refer to Altera Wiki http://www.alterawiki.com/wiki/epcs_based_remote_system_update_(rsu)_example_on_bemicro_sdk

I don't use remote system upgrade with NIOS, but at first sight you are setting the boot address right. Other parameters must be set, too. The watchdog must be e.g. explicitely disabled.

I didnt find, how to disable watchdog for Cyclone III (i have EP3C25) in altremote_update megafunction user guide.

The example should be fine, but i am not familiar with linux and script file, so my compilation in Quartus 12.0 finished with error:

Error (12006): Node instance "id_tcm_app_ram_32k" instantiates undefined entity "test_sys_top_qsys_id_tcm_app_ram_32k"

So, how to disable watchdog or how to start reconfiguration from another address than 0x0 ?

If it is not possible i can copy factory image 0x000000-0x100000 to second half of flash, then read bitstream from uart and download its to low half of flash ... and after this start reconfig.

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So, how to disable watchdog or how to start reconfiguration from another address than 0x0 ?

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For the parameters of altremote_update MF available for Cyclone III, please refer to table 8 of the most recent remote update ip core user guide. You should at least disable the Watchdog (provided it's not served in your application) and set the boot address (as you already do). The examples set also the osc_int and cd_early bit options, althoug it's probably not required. I didn't check, just performed the suggested actions.

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If it is not possible i can copy factory image 0x000000-0x100000 to second half of flash, then read bitstream from uart and download its to low half of flash ... and after this start reconfig.

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That's surely possible but not intended usage of remote system upgrade. If the action fails somehow, you end up with non-functional system and need to connect a JTAG programmer. The idea is to keep the factory image as safe fallback option.

Thanks, i again download last user guide, but it is same, which i have had ... www.altera.com/literature/ug/ug_altremote.pdf.

Table 8 is located from page 19 - 22, but which bit disable watchdog (in attachment).... ? I dont see this, so nothing, i appear AN603

www.altera.com/literature/an/an603.pdf

and now i can study all from this :) So i thing, that Altera hasn´t well described this megafunction and the example for nios would be useful for many people...

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but which bit disable watchdog

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The table tells that parameter 100 must be written to 0. AN603 documentation has even signal tap waveform of individual parameter read and write operations, but the parameter addresses are for Arria II.

Generally, you can do some debugging to find out what happens in your previously described test. You try to start the application image and it fails. But waht happens:

- no reconfig started at all

- reconfig with wrong start address

- reconfig with right address but invalid image

- reconfig with valid image but watchdog causes reboot

Thank you for your support. I have more errors in this project. The first it was wrong address - shift to the left not to the right - bad address=0x00400000, correct address=0x00040000 (i had have only one 0 more:)), bad number code for disable watchdog and when i erase and program the flash eprom it was neccessary to close flash eprom.

I first try it on board DE0 Nano, so i include my project, when is possible to switch two bitstreams (one start on 0x0 address and second start on 0x00100000). After this i copy to my board and now it works.:)

Jan Naceradsky, Czech Republic