Regional Clock, PLL (Arria V)

I was wandering how PLL can drive regional clock.

Looking at Arria V Handbook, I can see that B3 device has ,I suppose that TOP LEFT corner fPLL drive only regional clock in the region of the PLL so top left quadrant.

But what about the central PLL?

Can it drive all regions? Or in case of B3 device the TOP Central PLL can drive top left and top right region only?

Where can I check this information?

I was trying to see if I can see clock details in Chip Planner, but I can't succed.

Thank you