New Contributor
Super ContributorHi,
MAX 10 is basically a good choice for PFL II implementation. There are however no MAX 10 specific submodules in the IP core. It's not clear at first sight why PFL configuration function shouldn't be available e.g. with Cyclone 10 LP. I notice that also standard PFL IP doesn't provide configuration function for other devices than MAX II, MAX V or MAX 10. This isn't congruent to PFL User Guide that tells
"You can use the PFL IP core in Intel MAX® devices (Intel MAX 10, MAX II, and MAX V devices) or all other FPGAs to program flash memory devices efficiently through the JTAG interface and to control configuration from the
flash memory device to the Intel FPGA." https://docs.altera.com/r/docs/683698/21-1/parallel-flash-loader-intel-fpga-ip-user-guide
I was able to import MAX 10 PFL II IP files to a Cyclone 10 LP design and compile without errors. Unfortunately I have no test hardware to check the function.
Regards
Frank
New ContributorThank you. Is the reason why “FPGA Configuration” cannot be selected in the PFL II IP when using Cyclone 10 LP still unclear?
In general, is PFL‑based configuration not recommended when using Cyclone 10 LP?
Regular ContributorHi Mario,
Cyclone 10 LP is not an official supported external host for Agilex 5 Avalon‑ST when using PFL II. Supported hosts are MAX II, MAX V, MAX 10, or a microprocessor that streams the bitstream. Avalon-ST Configuration
Recommended approach: use a MAX 10 running PFL II to read flash and drive Avalon‑ST.
Can you still try Cyclone 10 LP as a host? Only as a custom, official implementation where you need to build the host logic yourself.
Regards,
Fakhrul
