Forum Discussion

mario's avatar
mario
Icon for New Contributor rankNew Contributor
13 days ago

Regarding Cyclone 10 LP AS Configuration Timing Parameters

We are currently planning to verify the configuration between Cyclone 10 LP and an external Flash ROM. In order to confirm whether the Flash side specifications (setup / hold, tSLCH, etc.) are satis...
Configuration
FakhrulA_altera's avatar
FakhrulA_altera
Icon for Regular Contributor rankRegular Contributor
4 days ago

Hi mario,

Thank you for your question.

For Cyclone 10 LP AS configuration mode, the public datasheet only specifies the AS DCLK frequency range. The documented DCLK range is 20 MHz to 40 MHz, with 33 MHz typical. Cyclone® 10 LP Device Datasheet

The specific timing items below are not separately specified in the Cyclone 10 LP datasheet:

  1. DCLK high time and low time minimum values
  2. Delay from DCLK edge to ASDO data change
  3. Time from nCSO Low to the first DCLK edge
  4. Time from the last DCLK edge to nCSO High

Because these values are not published, we cannot provide guaranteed min/max timing numbers for them.

For Flash ROM selection, please make sure the Flash device can support the Cyclone 10 LP AS DCLK frequency range, especially the maximum 40 MHz operating point. If your design requires guaranteed detailed pin timing, we recommend verifying this on the actual board or raising a formal support request for further review.

Best regards,
Fakhrul