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Altera_Forum
Honored Contributor
10 years agoIn the FPP with compression, typically the external host need 4x DCLK cycle to latch a byte into the FPGA (DCLK-to-DATA ratio of 4). In this case, the configuration time is expected longer.
You can consider to use the PFL with enhance bitstream compression and decompression feature to reduce the configuration time in FPP mode. For FPP with enhanced bitstream decompression enabled, the DCLK frequency is ×1 the data rate, thus the configuration time should be shorter. You can refer to the details from the PFL user guide: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_pfl.pdf