reduce labs in design

Question

Hi all!

This is the first time i use a CPLD and i run into a problem.

I have a lot of 4000 serie logic that i want to put into a CPLD. So i did copy my logic into schematic design and compiled it. I have a lot og i/o left and also a lot of macro cells but...... i am short 1 LAB.

I could not find anything on the forum to adres this problem so thats why i make this post.

Can anyone help me or explain to me how i might reduce the ammount of LAB's?

Thanks a lot!

altera_forum · Answer

LAB usage will depend on your source - so the way to reduce the LAB usage is to change the design

altera_forum · Answer

Is writing own VHDL code a good way to reduce the amount of LAB'S? I have a cd4013 and the set is always to low and data is always high in a part of the design. So that might help ?

altera_forum · Answer

If the code describes the same logic as the schematic, then you'll get the same problem. The schematic/code/whatever is not the problem. It's the design.

altera_forum · Answer

Well we tried to make the same logic using vhdl code and i use 1 lab less. Just because it does not have to look at a data and set signal.

altera_forum · Answer

--- Quote Start ---

Well we tried to make the same logic using vhdl code and i use 1 lab less. Just because it does not have to look at a data and set signal.

--- Quote End ---

That implies you changed the design - VHDL itself wasnt the fix

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reduce labs in design

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