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Altera_Forum
Honored Contributor
Honored Contributorreduce labs in design
Hi all!
This is the first time i use a CPLD and i run into a problem. I have a lot of 4000 serie logic that i want to put into a CPLD. So i did copy my logic into schematic design and compiled it. I have a lot og i/o left and also a lot of macro cells but...... i am short 1 LAB. I could not find anything on the forum to adres this problem so thats why i make this post. Can anyone help me or explain to me how i might reduce the ammount of LAB's? Thanks a lot!5 Replies
Altera_ForumLAB usage will depend on your source - so the way to reduce the LAB usage is to change the design
- Altera_Forum
Is writing own VHDL code a good way to reduce the amount of LAB'S? I have a cd4013 and the set is always to low and data is always high in a part of the design. So that might help ?
- Altera_Forum
If the code describes the same logic as the schematic, then you'll get the same problem. The schematic/code/whatever is not the problem. It's the design.
- Altera_Forum
Well we tried to make the same logic using vhdl code and i use 1 lab less. Just because it does not have to look at a data and set signal.
- Altera_Forum--- Quote Start --- Well we tried to make the same logic using vhdl code and i use 1 lab less. Just because it does not have to look at a data and set signal. --- Quote End --- That implies you changed the design - VHDL itself wasnt the fix
