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Altera_Forum
Honored Contributor
Honored Contributorreduce labs in design
Hi all! This is the first time i use a CPLD and i run into a problem. I have a lot of 4000 serie logic that i want to put into a CPLD. So i did copy my logic into schematic design and comp...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Well we tried to make the same logic using vhdl code and i use 1 lab less. Just because it does not have to look at a data and set signal. --- Quote End --- That implies you changed the design - VHDL itself wasnt the fix
