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Altera_Forum
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11 years ago

reduce labs in design

Hi all! This is the first time i use a CPLD and i run into a problem. I have a lot of 4000 serie logic that i want to put into a CPLD. So i did copy my logic into schematic design and comp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Is writing own VHDL code a good way to reduce the amount of LAB'S? I have a cd4013 and the set is always to low and data is always high in a part of the design. So that might help ?