Recovery Removal and multiclock IP

Thanks Kevin. I will have to figure out the SDC commands to narrow the path down, ideally something that just cuts thru the *dcfifo*aclr ports. My trouble is that I'm using SOPC to generate code. SOPC generates resets sync'd to each clock domain, and uses dcfifos in the clock-crossing bridge modules. So even if I find the generated reset signal for each clock domain, I don't want to ignore from clk_A_reset to ALL of the clk_B destinations, otherwise I risk becoming blind to any incorrect usage of clk_A_reset. (Not to mention having to remember to update the constraints everytime I change the SOPC connections.)

Since it's SOPC generated, I had hoped it would just generate something timing clean, and with the type of constraints you asked for in the altera support request (cut thru aclr, at least to rdclk domain). (eg: perhaps cut wherever they sync aclr internal to the module). I'd even prefer the solution in your previous post, to simply use separate clr inputs.

Anyway, it's reassuring to hear that adding false path constraints seems to be required in this situation.

I need to brush up on my SDC anyway (eg: how to make timing analysis catch the recovery violations even if we leave the read clk at 50MHz instead of 49MHz. It's scary that it reports the 50MHz version is timing clean when there's no expressed phase relationship between 50 & 100MHz clks.)