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Honored Contributor
Honored ContributorRecovery Removal and multiclock IP
I'm using ASI receiver IP that works with a lot of clock (135MHz, 337.5Mhz and 337.5Mhz shifted of 90°). All theese clock are done by the same PLL that is fed by a 27Mhz (that is the natural clock...
Altera_ForumHonored Contributor
Honored ContributorThanks Kevin, the example makes it very easy to discuss. I know this is an old thread, but can you post the changes that support mentions making to the .sdc? (Or any alternative solution you've found?)
Neither the kdb link nor the .sdc in the .qar seem to address the aclr reset input paths that you are talking about. (& that I care about :) ) The easiest way to reproduce the violation I'm concerned about is to use your fifo_test qar, but change the timing.sdc file to have a 49MHz clk_out (rd_clk) instead of 50MHz. When I run that thru Quartus 10.1, I get -0.7ns recover violation to wr_clk. If I also change aclr to use wr_rstn instead of rd_rstn, I get -1ns recovery violation to rd_clk. So, what SDC commands do you use to avoid these? **note: according to http://www.altera.com/literature/ug/ug_fifo.pdf, Quartus 8.1 and newer TimeQuest will automatically add the false paths mentioned in the kdb.** -Brian
