Recovery Removal and multiclock IP

I have had this issue as well in certain places, mainly the DDR2HP cores and the DCFIFO cores.

I wanted to reconfigure reset sequences on the DDR2HP cores when i shared multiple cores on a single IC. I just went into the files that handled them and routed certain signals to the top level and certain signals back into the core to be used as the reset.

For the DCFIFO core, i went into the medafunctions/dcfifo.tdf file and modified all of the aclr signals to include both a wr_aclr and a rd_aclr, mapped those to the top level, and then i can provide both a write reset and a read reset signal. Then i wrapped a library around them that looks just like the altera_mf_components library so i can choose which instance to use based on the included library. It has worked out well so far.

Usually the reset circuitry is not in an encrypted section of code, so it should be easy to modify the files you need. Just copy the library file into a new directory, make the changes, then include that file into your project so it gets used before the original library file does.

Good questions, and hope this helps a little slash shows incite into how i have been dealing with it. It would be nice if altera was better at bringing signals like resets and enabled to the top level and letting the user decide how to hook them up, but they also try to make the easiest to use cores. Give and take...

Kevin