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Altera_Forum
Honored Contributor
15 years agoSince I am not so good in VHDL , I would prefere a wiring diagram if possible. For me it is not clear how a 16kHz clock can generated based on the only 50 MHz clock available on MAXII.
Since I am not so good in VHDL , I would prefere a wiring diagram if possible. For me it is not clear how a 16kHz clock can generated based on the only 50 MHz clock available on MAXII.