Realization MFM de/en-Coder via MAXII

62,5uSec = 16kHz clock

the period is 10 times the clock

so you need a clock or an clock enable that is 1 every 62,5uSec

verilog HDL

reg [3:0] counter;

always @ ( posedge my16khzclock )

if ( counter === 4'd0 )

counter == 4'd9; // this reload the counter

else

counter <= counter - d'd1;

now you have a counter that counts down from 9 to 0 and then reloads to 9 again. that is your period of 625uSec, assuming you have a correct clock.

now the output signal, that could be a register or combinatorical

wire mypulse;

assign mypulse = !counter;

or

reg mypulse;

always @ ( posedge my16khzclock )

if ( counter === 4'd0 )

mypulse <= 1'b1;

else

mypulse <= 1'b0;

now mypulse should be 1 for a single my16khzclock cycle every 10 cycles.