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KJ's avatar
KJ
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14 days ago

Power and thermal characterization of Agilex 5

We are working on the power characterization of a design based on the Agilex5 E-series and I've come across a few questions I haven't been able to fully resolve from Altera's documentation. Would you...
Power
Farabi_Altera's avatar
Farabi_Altera
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13 days ago

Hello Chris, 

 

1- Typical static power model

i- When the typical static power model will be available? 

Ans: Please refer here Table 23

 

ii- access to pre-release model 

Ans: All the E-series power model is updated in 26.1

 

2- Power and Thermal Analyzer on empty design

i(a)- design use no DSP or RAM blocks

Ans: This is expected. Even no DSP or M20K blocks instantiated, the silicon physically contributes leakage/static power. 

 

i(b)- Which fabric component draw power significantly

Ans: clock input buffer, Global clock, configuration related circuitry, SDM, default termination, unused IO bank static leakage etc.IO is only one part of the contributors.

 

i(c) - what is included in miscellaneous category?

Ans:  SDM related circuit, Configuration circuit, Device management logic, power-monitoring circuit(POR), temperature/voltage sensing circuit, etc.

 

3- Can HPS and transceivers by fully powered down by disconnecting the power rails?

Ans: Basically yes, but why? you can choose device variance without HPS and without transceiver if you dont want this feature. This variance comes without HPS and transceivers. 

 

regards,
Farabi

 

 

 

  • KJ's avatar
    KJ
    Icon for New Contributor rankNew Contributor
    12 days ago

    Hi Farabi,

    Thank you for your answers. They are very useful.

    With regards to power consumption of uninstantiated DSP and M20K blocks, the report shows they also contribute to dynamic power consumption, as opposed to just leakage power. Could you clarify why?

    With regards to powering down HPS/transceivers, choosing the part that doesn't have those in the first place would be ideal, but not all fabric sizes for Agilex 5 E come with that configuration option, unfortunately. 

    Regards,

    Chris

    • Farabi_Altera's avatar
      Farabi_Altera
      Icon for Regular Contributor rankRegular Contributor
      8 days ago

      Hello Chris, 

       

      1- Power analyzer partitions device power into categories. Some infrastructure power may be allocated to DSP or RAM category even though no DSP arithmetic or memory read/write activity is occurring. 

      2- Even individual blocks are power-gated, the surrounding clocking and infrastructure networks still exist on the die. The analyzer may distribute a portion of this activity into DSP/RAM categories. 

      3- Power Analyzer includes small baseline dynamic values to account for device-level activity that cannot be cleanly assigned elsewhere. In nearly empty design, these baseline values can appear in the calcualtion. 

       

      regards,
      Farabi

    • Farabi_Altera's avatar
      Farabi_Altera
      Icon for Regular Contributor rankRegular Contributor
      6 days ago

      Hello Chris, 

       

      Do you have further question? 

       

      rgards,

      Farabi