Forum Discussion
New ContributorMarking codes of CY10CL040YF484
New ContributorDear Sir,
Please find the attached schematic
The cards in which JTAG error is coming in that TDO is not coming. in this card CONF_DONE pin always high and NCSO is "LOW" after programming in AS mode and NSTATUS is LOW. NCONFIG once program started its becoming LOWfor some time and then HIGHuntill proram and after Program over in AS mode.
and in working cards NSTATUS during Program LOW and after Program over it is HIGH. CONF_DONE is during Program LOW and after Program over it is HIGH. NCONFIG once program started its becoming LOW for some time and then HIGH untill proram and after Program over in AS mode.
please see my previous mail attached schematic and please see images attached . in working card DEVICE ID is coming and in bad card direct its telling JTAG error.
please see the attached images
VCCIO bank1 voltage is 3.3V only and VREF pins i am using them as i/o pins.
MSEL setting "0010" and nCE grounded with 10k resistor and connected to programmer 6th pin. with same download cable and same program i am loading in to good card and bad card.
TCK freq is 6MHZ waveform attached.
Regards
Suvarna
Regular ContributorHi Suvarna,
Thank you for the detailed results.
Because the same cable and programming file work on the good card, while the bad card does not return TDO or a device ID, the failure occurs at the JTAG communication stage before programming.
Please check the following on a failing card:
- For a single-device configuration, nCE must remain low and should be connected directly to GND. Please verify the voltage at the FPGA nCE pin during JTAG detection.
- Reduce the JTAG frequency from 6 MHz to 1 MHz, then compare TCK, TMS, TDI, and TDO directly at the FPGA pins on the good and bad cards.
- Check continuity and solder connections for the JTAG and configuration pins, especially TDO, nCE, nSTATUS, and CONF_DONE.
- Confirm that VCCINT, VCCA, and Bank 1 VCCIO remain within specification during JTAG detection.
For AS configuration, nSTATUS remaining low after programming indicates a configuration error. CONF_DONE remaining high throughout programming is also not the expected behavior. Please verify the pull-up and routing of nSTATUS and CONF_DONE, and compare DCLK, DATA0, and nCSO at the FPGA pins against the working card.
If these signals, power rails, and connections are confirmed correct but TDO remains inactive only on the affected devices, the next step is to contact the distributor for RMA or failure analysis.
Regards,
Fakhrul
- suvarna
Dear Sir,
I am unable to reduce JTAG frequency , i am using byte blaster i am loading the pof and sof files to the FPGA.
please see the attached image for device settings . i am not using init_done,dev_oe,dev_clrn and i conneted those signals to ground via zero ohms resistor.
the FPGA in the card Sl.No: 4 initially responded some pins functioned and some pins did not function. in the same card we replaced another FPGA and now config device programmed but FPGA not responding at all and jtag also error.
- suvarna
Dear SIr,
please see the previous reply as well as this one. what reason for FPGA is not wakening?
not responding.
