Forum Discussion
New ContributorLeakage Current in MAX 10 Bank 1A (ADC Bank)
New ContributorI would also appreciate the engineer’s input on this matter.
Regular ContributorHi y-fujiwara,
10M08DCF256I7G is a dual-supply compact device and does not include the ADC, so Bank 1A is a normal I/O bank. The ADC is on the analog ordering codes (DA or SA). I confirmed this in 10M08DC pin-out, Bank 1A has no ADC pins. It is a normal I/O bank, with the same leakage specification as Bank 8.
So, the lower voltage on Bank 1A is not caused by ADC pin leakage on this device.
Your divider (10 kohm / 3.6 kohm) has a source resistance of about 2.65 kohm. Bank 8 at 3.17 V is essentially the unloaded divider voltage (about 3.18 V). Bank 1A at 3.06 V is about 0.11 V lower, which implies about 42 uA into that pin. That is above the +/-10 uA normal limit, so Bank 1A is drawing extra current in this condition.
Please check these three items:
- VCCIO of Bank 1A compared with Bank 8. If the pin voltage is above that bank's VCCIO, the clamp diode is on. The datasheet states that a higher current can be observed when the diode is on.
- Both banks are fully powered when you measure. The +/-10 uA values are for normal operation and can be different during power-up.
- The Quartus assignment for the Bank 1A pin: input only, with bus-hold, weak pull-up, and weak pull-down off, and the pin is not also driven as an output.
If Bank 1A VCCIO is at least 3.3 V, the clamp is off, and the pin is a plain input, about 42 uA is outside the published +/-10 uA limit.
References:
- The DC and DA ordering codes are in the MAX 10 FPGA Device Overview (683658), in the ordering-information section: https://docs.altera.com/r/docs/683658/current/max-10-fpga-device-overview/max-10-device-ordering-information
- The feature table that lists the integrated ADC only under the Analog option is here: https://docs.altera.com/r/docs/683658/current/max-10-fpga-device-overview/max-10-device-feature-options
- y-fujiwara
1. VCCIO of Bank 1A Compared to Bank 8
Both banks share the same 3.3 V power supply, and we confirmed that the voltage measured directly at the pins is 3.3 V for both banks.
2. Confirmation That Both Banks Are Properly Powered During Measurement
The measurements were taken after boot completion, when the device was in a normal operating state. We also confirmed that 3.3 V was applied directly to the pins of both banks.
3. Quartus Settings for Bank 1A Pins
Bank 1A uses the same settings as Bank 8, as follows:
I/O Standard: 3.3 V LVTTL
Direction: Input
Internal Pull-Up/Pull-Down: OFF
In addition, as part of our investigation, we reduced the resistor values in the voltage divider and measured the voltage again. We confirmed that the voltage deviation became smaller.
12 V, 10 kΩ / 3.6 kΩ
Calculated voltage: 3.18 V
Measured voltage: 3.06 V (−0.12 V)
12 V, 1.6 kΩ / 0.56 kΩ
Calculated voltage: 3.11 V
Measured voltage: 3.10 V (−0.01 V)
