Forum Discussion

linhz0hz's avatar
linhz0hz
Icon for New Contributor rankNew Contributor
15 days ago

IO speed limit while implementing high resolution PWM on Cyclone 10

I would like to implement high resolution PWM on a Cyclone 10 LP. One simple approach I have is running the IO at double data rate for a high possible switching frequency. However as the single ende...
Generic Io
Programmable Logic Device
linhz0hz's avatar
linhz0hz
Icon for New Contributor rankNew Contributor
6 days ago

Thanks for the response. It seems fine for single ended output, I got issue in timing analysis but the entire compilation finished nevertheless. However if I use differential signaling (for example lvds) I got 

Error (176060): The transmitter driving I/O pin pwm_out at data rate 800 Mbps exceeds the maximum allowed data rate of 640 Mbps for LVDS output 

In the fitter stage and cannot finish the compilation. As I said I am oversampling the signal so the actual switching rate is much lower. Is there a way to suppress this and keep compilation going?

Thanks 

AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
1 day ago

No, unfortunately, you can't suppress the fitter error in Quartus. The fitter enforces a device's physical limit for LVDS outputs (e.g., 640 Mb/s). I guess that the error indicates a physical capability check of the I/O standard and is not a timing-only warning that can be silenced.

 

Hence, if signal integrity and board routing allow, switch the pin I/O standard to a single‑ended standard (e.g., LVTTL/3.3V) so the fitter won’t apply the LVDS hard limit. You have already seen that this compiles (with timing warnings).