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y-fujiwara
New Contributor
New ContributorInvestigation of HIGH-Level Voltage Fluctuations on MAX 10 3.3 V LVTTL Output Signals
We are investigating the cause of fluctuations in the HIGH-level voltage of a 3.3 V LVTTL output signal from the MAX 10 FPGA. Device Part Number: 10M08DCF256I7G HIGH-Level Voltage: 2.8 V to 3.3 V ...
y-fujiwaraNew Contributor
New ContributorAs you mentioned, this phenomenon does not affect the circuit's operation.
We investigated it as a precaution because we noticed an unusual feature in the waveform.
The phenomenon appears to be caused by internal noise coupling within the IC. Therefore, if there are no effective countermeasures available, we believe it should be acceptable to leave the design as it is.
AqidAyman_Altera
Regular Contributor
Regular ContributorI understand. Thank you for the clarification.
From the MAX 10 side, there are several signal integrity levers worth examining if you have the chance to do it as a software-only change without board respins required.
Two immediate knobs to try:
- Reduce drive strength. The output buffer for each MAX 10 I/O pin has a programmable current strength control. For 3.3 V LVTTL, the available settings are 8 mA and 4 mA. Programmable Current Strength Try to drop from 8 mA to 4 mA.
- Enable slow slew rate. Slow slew rate reduces system noise and crosstalk, but adds a nominal delay to the rising and falling edges. MAX 10 General Purpose I/O User Guide If timing margin permits, this is a low-risk change that you can experiment.
