Re: Inquiry Regarding Cyclone V IBIS Model Definitions and Updates

Dear Aqid,

Thank you very much for your continued support and for checking with the internal team.

I apologize in advance if my question seems a bit basic — I’m not very familiar with the detailed relationship between HSPICE and IBIS models, so I may be misunderstanding something fundamental.

To clarify your latest message:
You mentioned that the HSPICE models for 3.3V LVCMOS (2mA) and 3.3V LVTTL (16mA) use the same bit settings, and therefore the corresponding IBIS models are expected to behave similarly.

Could you please confirm whether this means:

• The HSPICE model is correct, and the IBIS models are also correct because they are based on that valid configuration?
  or
• The HSPICE model contains a mistake in the bit settings, and as a result, the IBIS models are also incorrect due to inheriting that issue?

I just want to make sure I understand whether the similarity in IBIS behavior is intentional and correct, or unintentional and due to an error in the underlying HSPICE model.

Additionally, I am planning to use the following I/O standards in my simulations:

• 3.3V LVCMOS (lvcmos_*)
• 3.3V LVTTL (lvttl_*)
• SSTL-135 (sstl135_*)
• Differential SSTL-135 (dsstl135_*)

Could you please advise which of these models are considered valid and reliable for signal integrity simulation purposes?

Thank you again for your patience and clarification.

Best regards,
Ryusuke YOKOYA