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RyusukeYOKOYA's avatar
RyusukeYOKOYA
Icon for New Contributor rankNew Contributor
1 year ago

Re: Inquiry Regarding Cyclone V IBIS Model Definitions and Updates

Dear Intel Support Team, I hope this message finds you well. I am currently conducting IBIS simulations for the Cyclone V FPGA, specifically for the part number 5CGXFC9C6F23, and I have a few quest...
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AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hello,


Based on my findings and discussion with internal team, the IBIS models below are expected to exhibit similar behaviour because, based on the HSPICE models for Cyclone V device, the bit settings for the 2mA current strength of 3.3 V LVCMOS and the 16mA current strength of 3.3 V LVTTL are the same. You can refer to the drive_select_IO.lib file located in the lib folder of the CV_GPIO_hspice_model_v2p0 for the bit settings for each drive strength setting.


lvcmos_rtpio_d2s1 and lvttl_rtpio_d16s1

lvcmos_rtpio_d2s1_p and lvttl_rtpio_d16s1_p