Occasional Contributor
Hi, Richard
Thank you. I have already solved the problem.
Super ContributorI'm not sure what "the image would occasionally and intermittently split" means as the issue, but is your design meeting timing? How fast are you running it?
Like it says there, best speed is inserting an additional register. Are you taking into account this extra cycle of latency elsewhere in your design?
Occasional ContributorHi
My goal is to design an SCFIFO using an FPGA to replace an obsolete component. I looked into the issue and consulted AI, which aligned with your point: adopting the "best speed" optimization would insert an additional register and introduce an extra cycle of latency.
However, since the firmware is completely fixed and cannot be modified on my end, managing this extra latency solely within the FPGA logic is quite challenging for me.
Given our application—where the FPGA receives image data from a sensor and forwards it to a PC via a USB interface—I believe the "small area" configuration might be a better fit for our requirements.
My operating frequency is 48 MHz.
