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Thulasi's avatar
Thulasi
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1 month ago

Global Clock & Regional clock inputs in Agilex M FPGA

Hi, Kindly answer the following query related to USB PHY connection to MAX10 in Agilex I series FPGA design. In the reference design, why USB phy is connected to BMC(MAX10) in PCIe based card based...
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Thulasi's avatar
Thulasi
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16 days ago

Hi,

1. Why do we need to provide both a JTAG header and a USB connector (along with its supporting circuitry) for JTAG access?

2. Can we eliminate the USB circuitry and provide only the JTAG header?

3. Alternatively, can we remove the JTAG header and retain only the USB connector and its associated circuitry?

4. Why is an on-board USB-Blaster II required? Wouldn't a standard JTAG header alone be sufficient for programming and debugging?

Regards,

Thulasi

 

 

AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
14 days ago

Hi Thulasi,

 

As an evaluation kit, we want to provide both JTAG experience to the customer. However, it is dependent on your requirement to not use the USB circuitry but please ensure you have the USB Blaster IP in order to use JTAG from USB connector.

 

Regards,
Aqid