Forum Discussion
Occasional ContributorCyclone 10 GX AS x4 Configuration Compatibility with Infineon S25FS512S (Custom Flash Definition)
Occasional ContributorHi Farabi,
Thanks for the detailed response.
I have applied the flash configuration settings and also verified the AS x4 configuration sequence using a Saleae logic analyzer.
For the S25FS512S, I have configured the non-volatile configuration registers as follows:
- CR1NV = 0x02
- CR2NV = 0x88
- CR3NV = 0x08
My understanding of these settings is:
- CR1NV = 0x02 → Quad I/O enabled.
- CR2NV = 0x88 → 4-byte address mode enabled (CR2NV[7] = 1) with 8 read-latency/dummy cycles (CR2NV[3:0] = 1000b), while QPI remains disabled (CR2NV[6] = 0).
- CR3NV = 0x08 → 4-KB erase disabled, corresponding to the uniform-sector architecture with 256-KB sectors.
The S25FS512S datasheet confirms that CR2NV[7] controls 3-/4-byte addressing and CR2NV[3:0] controls read latency. It also shows that CR2NV[6] is the QPI enable bit.
I am configuring these registers during the flash initialization sequence using WRAR (71h). The sequence is:
Read Status Register
↓
Read JEDEC ID (9Fh)
↓
Enable 4-byte addressing (B7h)
↓
Wait for completion
↓
WREN (06h)
↓
WRAR (71h) → CR1NV = 02h
↓
Wait for completion
↓
WREN (06h)
↓
WRAR (71h) → CR2NV = 88h
↓
Wait for completion
↓
WREN (06h)
↓
WRAR (71h) → CR3NV = 08h
↓
Wait for completionThe corresponding commands in my Custom Flash Definition are:
- WRAR 71h + Address 0x00000002 + Data 0x02
- WRAR 71h + Address 0x00000003 + Data 0x88
- WRAR 71h + Address 0x00000004 + Data 0x08
I also verify that the write operation has completed after each register write.
However, even with these settings, AS x4 configuration is still not successful.
Quad I/O dummy-clock settings tested
I have tried the following configurations in Convert Programming File:
Test 1
- Quad I/O dummy clock = 10
- Single I/O dummy clock = 8
The FPGA did not configure successfully in AS x4.
Test 2
- Quad I/O dummy clock = 8
- Single I/O dummy clock = 8
The FPGA also did not configure successfully in AS x4.
Based on your previous explanation that the Cyclone 10 GX controller uses 10 dummy clocks and that the compensation should be:
Quad I/O dummy clocks = flash latency + 2
I understand that, with the S25FS512S configured for 8 latency cycles, the Convert Programming File Quad I/O dummy-clock setting should be 10. I have already tested this setting, but the configuration still fails.
Saleae capture observation
I also analyzed the actual AS x4 configuration sequence in more detail.
For example, my image starts at:
Image start address = 0x00040000
The configuration sequence observed on the Saleae capture is approximately:
9Fh
Read Device ID
↓
0Bh
Single I/O Fast Read
Address = 0x00000000
↓
0Bh
Single I/O Fast Read
Address = 0x00040000
↓
EBh
Quad I/O Read
Address = 0x000403B8
↓
Configuration does not complete
↓
9Fh
Read Device ID again
↓
0Bh / EBh accesses repeatTherefore, the first EBh access that I observe is:
0x000403B8
which corresponds to:
0x000403B8 - 0x00040000 = 0x3B8
From your previous explanation, I understand that this offset can vary depending on the Quartus version, tool-generated image structure, device, and other configuration parameters. I also understand from your latest response that the initial 0Bh read is expected to obtain boot/header information before the controller switches to the Quad I/O read for the configuration data.
Clarification requested
Since the flash is configured with:
- CR1NV = 0x02
- CR2NV = 0x88
- CR3NV = 0x08
and I have already tested the recommended:
- Quad I/O dummy clock = 10
- Single I/O dummy clock = 8
but AS x4 configuration is still failing, could you please clarify the following?
- For S25FS512S, is CR2NV = 0x88 the correct non-volatile setting for AS x4 / 1-4-4 operation?
- According to the S25FS512S datasheet, CR2NV[7] = 1 enables 4-byte addressing and CR2NV[3:0] = 8 selects 8 read-latency cycles, while CR2NV[6] = 0 keeps the device in legacy SPI mode.
- Should I verify the actual CR1V/CR2V/CR3V values after power-up, rather than only verifying that the non-volatile register programming completed?
- Since the recommended Quad I/O dummy-clock value of 10 has already been tested and the configuration still fails, is there another S25FS512S configuration requirement that needs to be considered for the EBh transaction, particularly regarding the mode-cycle requirement?
- Regarding the observed:
- Image base = 0x00040000
- EBh address = 0x000403B8
- Offset = 0x3B8
- should the +2 compensation be applied at which location to work as expected?
- on memory at address 0x000403B8 or 0x00040000
Thanks,
Sumanth Srinivas
Regular ContributorHello Sumanth,
Thank you for providing the detailed logic analyzer observations and test environment context. Below are the clarifications and answers to your questions regarding the Cyclone 10 GX Active Serial x4 (AS x4) configuration behavior with the Infineon S25FS512S flash.
1. Does the Cyclone 10 GX configuration controller support transmitting the mandatory Mode Byte required by the EBh (Quad I/O Read) command?
No. The Cyclone 10 GX hard configuration controller (Control Block) does not generate or transmit a separate Mode Byte (also known as continuous read / XIP bits, M[7:0]) during the 0xEB (Quad I/O Fast Read) command sequence.
During Active Serial x4 configuration, the hardwired state machine inside the Cyclone 10 GX Control Block issues the following standard read transaction:
Opcode: 0xEB (1 line, 8 clock cycles)
Address: 4-byte / 32-bit address (4 lines, 8 clock cycles)
Dummy Clock Cycles: Fixed/configured clock cycles on DCLK (the FPGA does not drive active mode bits during these cycles)
Data Phase: Reads configuration bitstream data on DATA[3:0]
Because the FPGA configuration controller treats the cycles immediately following the address purely as wait/dummy cycles, it does not transmit the 8-bit mode byte pattern (M[7:0], which occupies 2 clock cycles across 4 I/O lines) required by the Infineon S25FS512S protocol.
2. Is this a known limitation of the Cyclone 10 GX configuration controller or Quartus Programmer?
This is a hardware controller architectural characteristic/limitation of the Cyclone 10 GX Control Block, not a limitation of the Quartus Programmer tool.
The Quartus Programmer is solely responsible for generating the programming image (.jic / .rpd) and programming the flash via JTAG using the Serial Flash Loader (SFL) IP.
Once programming is complete and the FPGA initiates configuration (upon power-up or nCONFIG pulse), the hard configuration engine in the Cyclone 10 GX acts as the SPI master.
The Cyclone 10 GX configuration controller was architected based on standard SPI NOR protocols (such as Micron and EPCQ-L devices), where random reads do not require a separate mode byte between the address and dummy clock cycles.
On the Infineon S25FS512S, the 0xEB command expects 2 mode cycles (8 bits on 4 lines) immediately following the address, followed by the programmed dummy/latency cycles. When the FPGA does not explicitly drive these mode cycles, the flash interprets the initial clock cycles differently or delays valid data output by 2 clock cycles relative to what the FPGA controller expects, resulting in bitstream misalignment and configuration failure.
3. Is there any supported method to modify the Quad I/O Read command sequence in the Custom Flash Definition?
No. The Custom Flash Definition XML file (used in the Quartus Programmer and Convert Programming Files based on AN229767 and Altera application notes) defines the JTAG programming parameters for the SFL IP (e.g., initialization sequences, register writes, page programming, sector erase, and verification).
It cannot modify, patch, or reprogram the hardwired configuration controller state machine inside the Cyclone 10 GX silicon. The read opcode (0x0B for AS x1, 0xEB for AS x4) and the protocol sequence issued by the FPGA during configuration are fixed in hardware.
4. Has Altera validated any Custom Flash Definition for the S25FS512S that can be shared as a reference?
Altera has not officially validated the Infineon/Cypress S25FS512S for Cyclone 10 GX Active Serial x4 configuration.
However, Altera provides a validated reference implementation for the newer Infineon/Cypress Semper family—specifically the Cypress S25HS512T with Cyclone 10 GX—in AN 1013: Using Generic QSPI Flash on Control Block-Based Devices (Section 6.1).
While the S25HS512T uses standard WRSR (0x01) register programming rather than WRAR (0x71), the configuration requirements outlined in AN 1013 apply to all control block-based devices using 1.8V 512Mb flash:
Key Technical Requirements & Recommendations
Disable EPCS/EPCQ ID Check (Mandatory):
In the Quartus Convert Programming Files tool, navigate to Advanced Options and enable "Disable EPCS/EPCQ ID check".
If this check is not disabled, the Cyclone 10 GX configuration controller expects an Altera-specific Silicon ID and aborts configuration after reading the JEDEC ID (0x9F), even if the flash is correctly programmed.
Dummy Clock Compensation Formula:
In the Infineon S25FS512S, the 0xEB command requires 2 Mode cycles (8 bits over 4 lines) followed by $N$ latency cycles configured in CR2NV[3:0].
To account for the 2 mode cycles when configuring Convert Programming Files: $$\text{Quad I/O Dummy Clocks} = \text{Flash Latency Cycles} + 2$$
For example, if CR2NV[3:0] is set to 8 latency cycles, the Quad I/O mode dummy clock parameter in Convert Programming Files must be set to 10. If CR2NV[3:0] is set to 6 latency cycles, the dummy clock setting should be 8.
Non-Volatile Register Settings for S25FS512S:
CR1NV = 0x02: Enables Quad I/O (QUAD bit = 1).
CR2NV = 0x88: Enables 4-byte addressing on power-up (bit 7 = 1) and sets latency code to 8 cycles (CR2NV[3:0] = 1000b), while keeping QPI disabled (bit 6 = 0). Note: Cyclone 10 GX requires 4-byte addressing upon power-up for flash densities >128 Mb (AN 1013, Section 3.2.2).
CR3NV = 0x08: Configures uniform 256-KB sector architecture (UNHYSA bit = 1) to eliminate hybrid 4-KB parameter sectors.
Recommended Workarounds / Path Forward:
Use Active Serial x1 (AS x1): Because AS x1 uses standard Fast Read (0x0B) with 8 dummy cycles and does not require mode cycles, it is fully compatible with the S25FS512S and avoids the Quad I/O mode byte incompatibility.
Supported Flash Alternatives: For applications requiring full Active Serial x4 bandwidth and guaranteed compatibility, consider selecting a tested third-party flash device from the Altera Device Configuration Support Center, such as the Cypress S25HS512T (documented in AN 1013) or supported Micron MT25QU / Macronix devices.
Best regards,
Farabi
