CLa_R
Occasional Contributor
Occasional ContributorConfig pins as normal IO pins
I would like to use JTAGEN, DEV_CLRn, DEV_OE and CONFIG_SEL pins, as normal IO pins, is it possible? To be able to do it do I have to create an external circuit or is only a quartus II configuration ...
Well, for reference I have about two dozen Altera FPGA production designs I have done over that last two decades, and never have I reused the configuration/status pins as normal I/O, or the JTAG pins either. They are all dedicated to their specific functions. If I needed more I/O, I went to either a larger package with more I/O capability, or found some way to multiplex existing I/Os (like using an external 8bit shift register device as an I/O expander, for example). Again just my 2c.
