Can I synthesize HDL, obtained as a result of DPC++ compilation, in Vivado for Xilinx FPGA?

I solved the issue myself.

I cannot do comparasion of those HLS tool because those are under agreements what don't allow use output (HDL) of the tools of someone provider to programm FPGA another provider.

My short interpretation of Intel agreement: output files of icpx compiler can be used only for programming Intel FPGA.

Intel agreement cite: "Your use of Intel Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Intel MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors".
Source of Intel agreement: commentaries in first lines of HDL files obtained using icpx compiler on oneAPI platform.

My short interpretation of Xilinx agreement: you cannot use Xilinx software to develop projects for devices other than Xilinx devices.

Xilinx agreement cite: "4. Restrictions. (a) Special Use Restrictions. No right is granted hereunder to use the Software or any Bitstream generated by use of the Software to program or develop designs for non-Xilinx Devices".
Source of Xilinx agreement: https://download.amd.com/docnav/documents/eula/end-user-license-agreement_2016.2.pdf.

Although, it's interesting that Vivado HLS output (HDL) can be used for succefull pragramming Intel FPGA. Source: https://support.xilinx.com/s/question/0D52E00006hpUOMSA2/transfer-the-hls-generated-veriloghdl-to-alteras-fpga?language=en_US.