Agilex 7 R-Tile RES FPGA – CXL Device Enumeration Failure with CXL IP Design Example

Q24.1 is not able to generate the ED for your target OPN. The Agilex 7 I-series dev kit has different memory arrangement for power solution 1 dev kit and power solution 2 dev kit. 

Please provide me your qsf and constraints/qsf_device_pinout.tcl. Thanks.

What's the original Quartus version you used for generating the example? 

Regards,

Rong