Altera_Forum
Honored Contributor
Honored ContributorRaw binary file format
Hi all,
I'm looking for documentation for the Raw binary file format and Tabular Text file format. Is this freely available, or will I have to talk to Altera directly?Forum Discussion
15 Replies
Altera_ForumRBF is just a simple binary format, that You can upload using simple serialization mechanism (e.g. SPI: SCK->DCLK, MOSI->DATA0). Except You need to do a byte-reverse before sending.
- Altera_Forum
I suppose I want to ask if there's an order to the bytes. What do the bytes refer to?
Which switch blocks do they refer to? background information: I'm interested in SEU effects on the configuration bits of the FPGA and verifying possible changes. I understand that there is a level of encryption applied to the raw binary format, but I am lead to assume that this is done during the download process. Based on this fact, the rbf is not encrypted. Is any of this correct? - Altera_Forum
The meaning of the configuration bitstream is undocumented. Besides a simple optional compression and a CRC consistency check, the configuration data can be expected as an image of various configuration bits distributed over the FPGA chip. Encryption is pointless without a key, you can review the configuration mechanism of Cyclone III LS familiy that provides AES encrypted configuration.
Although configuration data is quite complex, scientific studies have shown, that it's basically possible to reveal gate level logic information from it. I think, the topic has been discussed at Altera forum before. - Altera_Forum
Is the bitstream interally documented? (i.e. would require an agreement between my university and Altera)
I am writing a masters' thesis on SEU mitigation for safety-critical FPGA applications in regards to interconnect switches. The current CRC calculation rates are far too slow for our purposes. --- Quote Start --- Although configuration data is quite complex, scientific studies have shown, that it's basically possible to reveal gate level logic information from it. I think, the topic has been discussed at Altera forum before. --- Quote End --- Is there a link to this discussion? my searches yield back nothing. I am aware that it is possible to reverse-engineer netlist information from the bitstream, but this is not my purpose. - Altera_Forum
I'm not sure where I found the discussion. Here's one of the related papers.
- Altera_Forum
Thanks for trying to help.
I read this paper 1 year ago, and I was hoping for different news. Since this is a safety-critical (Nuclear power) application, we need to be able to verify that the bitstream and the netlist show the exact circuit layout. This is in addition to providing soft SEU mitigation techniques. All of this is to prove that there is no single point of failure in the FPGA tool. - Altera_Forum
In addition there have been a discussion at ulogic.com about how to apply the method discussed in the paper to Altera FPGAs. I guess you know it too.
- Altera_Forum
I am unable to find this discussion on ulogic.com as it links to a real estate website, but thanks for trying to help.
- Altera_Forum
Just to conclude this discussion, I've decided to use the Versatile Place and Route tool (VPR) made by Vaughn Betz from U of Toronto. This meets my need without resorting to the altera bitstream format.
- Altera_Forum
Hello
I am working with my mater thesis. I was wondering if you found a way to compile a project for an Altera FPGA with VTR and migrate to Quartus so you can can make the sof file. Thank you Dimitrios Agiakatsikas
