Raw binary file format

Is the bitstream interally documented? (i.e. would require an agreement between my university and Altera)

I am writing a masters' thesis on SEU mitigation for safety-critical FPGA applications in regards to interconnect switches. The current CRC calculation rates are far too slow for our purposes.

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Although configuration data is quite complex, scientific studies have shown, that it's basically possible to reveal gate level logic information from it. I think, the topic has been discussed at Altera forum before.

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Is there a link to this discussion? my searches yield back nothing. I am aware that it is possible to reverse-engineer netlist information from the bitstream, but this is not my purpose.